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Altera_Forum
Honored Contributor
Honored ContributorGlobal Variables in VHDL
Hello, I am told that the 2008 VHDL allows one to use global variables. Does anyone have nay example code that would demonstrate this? I am interested in any kind of feedback I can get from th...
Altera_ForumHonored Contributor
Honored Contributorif its for simulation, then theres no problem, and encouraged. You can use the heirarchical access (added in VHDL 2008) to get at them all from the testbench, so theres no need to modify your code. You will need modelsim 10+ though.
If its for inside an fpga - impossible. You'll need to do things properly and pass all the information through the port maps.
