Global Variables in VHDL

Do you mean global signals? I've heard of this too and thought someone told me they had it working, but I never tried it. I'd also be curious if there's anything similar for Verilog? I think it's a very dangerous tool, as the lazy engineer could start passing new signals around globally rather than modifying all the port lists, component declaration, but I think that would make debug extrenly difficult. But I think it would be fantastic for debugging, temporarily getting signals from other hierarchies, and could probably be used for general coding if well disciplined. (I'd also be curious if it works with Incremental Compilation?)