ap_mercy
New Contributor
New ContributorGetting error on mSGDMA IP
Im trying to follow the example in this page with 2 mSGDMAs: https://blog.reds.ch/?p=835
when i run synthesis I get the below error:
Forum Discussion
ap_mercyNew Contributor
New ContributorHello, thanks for your response. This example seems like an overkill for what what I'm trying to accomplish. I tried the example from https://blog.reds.ch/?p=835 on the latest quartus pro and still get the same error with mSGDMA IP. Is there an example that demonstrates only uses mSGDMA similar to what's on that (https://blog.reds.ch/?p=835) website?
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
For Stratix 10 there are non simple example design, however it is quite straightforward to port below design of the Arria 10 to the Stratix 10 below:
https://fpgacloud.intel.com/devstore/platform/17.1.0/Pro/arria-10-nios-ii-simple-socket-server-design-example/
- ap_mercy
That link didn't work
