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Altera_Forum's avatar
Altera_Forum
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14 years ago

get_cells usage

I am having problemunderstanding the get_cells command usage and results in Altera ( I am familar with the command in Primetime)

When I run this I get...

query_collection [get_cells ]

Info: Returned collection objects are limited by the default setting limit, 20

clk_sys WideOr0~0 pll_lock_mux~0 rtl~0 rtl~16 rtl~17 rtl~18 rtl~19 rtl~20 rtl~21 rtl~22 LEDOUT_GRN~0_wirecell LEDOUT_GRN~1_wirecell ~QUARTUS_CREATED_GND~I altera_internal_jtag XAUI_TX[0]~output XAUI_TX[1]~output XAUI_TX[2]~output XAUI_TX[3]~output LEDOUT_GRN[0]~output

They dont look like fpga top cells to me but wires and maybe pins.

ARe wires and pins considered cells to Altera?

Also when I run this I get....

foreach_in_collection asgn [get_cells *] {

puts $asgn> }

cell_43578

cell_44306

cell_45282

cell_59634

cell_59636

cell_59638

Why is the result different?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Those are cells. If you find them in the Chip Planner, they will be LUTs, FFs, and they will have pins on them. I'm guessing for the latter question, you need to run get_cell_info on each one. query_collection is probably assuming you want the name.