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Altera_Forum's avatar
Altera_Forum
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8 years ago

Generate flip-flop level RTL schematic

Hello, Quartus can generate RTL view, but using its LUT as primitive. ModelSim integrated into Quartus just don’t give RTL-like view. For learning VHDL basics, is there any configuration...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Your code didn't have a flip flop in it. Just a latch that had to be emulated with luts. You want the map view to see the most primitive level. An FPGA is all luts and registers. That's as primitive as it gets on anfpga