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Altera_Forum's avatar
Altera_Forum
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8 years ago

Generate flip-flop level RTL schematic

Hello, Quartus can generate RTL view, but using its LUT as primitive. ModelSim integrated into Quartus just don’t give RTL-like view. For learning VHDL basics, is there any configuration...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The picture you have posted are from ISE, which is Xilinx compilation software, not Quartus.

Modelsim wont give an RTL view, because it simulates your HDL code as is, it doesnt know about or care what the logic will be.