Gate level simulation of clock-less design

Thanks for the hint about the initialization! Now, however, ModelSim prompts an error after the reset signal goes down.

The error is "Error: (vsim-3601) Iteration limit reached at time 50 ps," which is probably due to the closed loop that is not supposed to be in a regular design.

FvM, you are right, a simulation based entirely on timing makes no sense for me. I thought that the gate level simulator is based on analog models for the gates, similar to a SPICE model. But, the simulation is only based on timing, right?

Then, I need to try something else anyway.