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Altera_Forum
Honored Contributor
Honored ContributorGate level simulation of clock-less design
I implement logic designs without clocks, which are non-deterministic systems for research purposes. Do you know if Gate Level Simulation with ModelSim is suitable for clock-less designs? For e...
Altera_ForumHonored Contributor
Honored ContributorThanks Rysc! I am running the gate level simulation now. The problem is, though, that it gives me values of "x" because inv[2:0] is not initialized. But, "inv" is a wire, so I cannot initialize it. I am doubting if this kind of simulation is working for me.
