Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Gate level simulation of clock-less design

I implement logic designs without clocks, which are non-deterministic systems for research purposes. Do you know if Gate Level Simulation with ModelSim is suitable for clock-less designs? For e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks Rysc! I am running the gate level simulation now. The problem is, though, that it gives me values of "x" because inv[2:0] is not initialized. But, "inv" is a wire, so I cannot initialize it. I am doubting if this kind of simulation is working for me.