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Altera_Forum
Honored Contributor
Honored ContributorGate level simulation of clock-less design
I implement logic designs without clocks, which are non-deterministic systems for research purposes. Do you know if Gate Level Simulation with ModelSim is suitable for clock-less designs? For e...
Altera_ForumHonored Contributor
Honored ContributorYes, it should show what you want. Note the timing delays are not nominal, i.e. if using the slow timing model(which is the most common) then all delays will be the slowest possible. Hardware will probably run considerably faster. Depending on your goals, that may or may not be a problem. (I believe newer devices don't have gate-level sims either, so you have to target something older...)
