Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

FT232RL as a clock for a Acex EP1K50TC144-3 fpga

Hi, This is my first post on the Altera forum :) I don't know if there is someone who has knowledge using an "old" Acex EP1K50TC144-3 fpga. I'm using a FT232RL chip which is capable o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Alex,

I had contact with FTDI support and the solution was to drive the I/O with higher current setting in the FT232RL EEPROM configuration.

Got no PULL-UP and the clock is running 48Mhz and connected to both 125, 126 pins. Signal is divided and set on output pin 51. This pin 51 is external routed to pin 55.

Don't know if it works with a PULL-UP?

Indeed, -3 part doesn't support the ClockLock/ClockBoost circuit and PLL.

Thanks for the reply!