FSM problem

The purspose of this process with a single constant assignment isn't well understandable, but because xy_reg is also assigned in the process FSM1, it's causing a "multiple driver" error. If you feel a need for multiple concurrent assignments to xy_reg, they have to be placed inside FSM1. For the general rules for signal assignments, consult a VHDL text book or tutorial.

Game: process (clk)
  begin
    if clk'event and clk = '1' then
      xy_reg(1,1) <= '1';^
    end if;
  end process Game;