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Altera_Forum
Honored Contributor
Honored ContributorFSM problem
Heyy I'm trying to make a video game in vhdl on de0 board and I need help about the following FSM. No error or warning. Does anyone notice a mistake?? thankss. type XY_REG_TYPE is array (0 ...
Altera_ForumHonored Contributor
Honored ContributorThis reminds me of an interview question when the man in power asked me why I used integer for my counters, and that I should have used unsigned. I firmly replied that constrained integers, or signed or unsigned or std_logic eventually are translated by compiler to buses. We either trust the tools or give up.
The above state machine looks to me well coded and too professional for a beginner. The problem itself is not stated. Is it used as it should be integrated correctly in the project...
