Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFrequency Divider Timing Req. Never Met
I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_ForumHonored Contributor
Honored ContributorYou didn't tell about the purpose of the divided clock in your design. Isn't it possible to use clkout as a clock enable instead of an actual clock? If I understand right, it's already active for one clkin cycle, as required for a clock enable in the clkin domain.
