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Altera_Forum
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14 years ago

Frequency Divider Timing Req. Never Met

I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Why doesn't it fail? When you launch TimeQuest and right click on the failing domain and do report_timing with detail set to full_path, what does it look like? What's the setup relationship?

You're clock rate is probably already really slow. This circuit should run really fast. So it should work, but something in the constraints, layout, etc. is not correct. You need to debug the timing report since it gives all of that information.