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Altera_Forum
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15 years ago

Frame buffer IP

We use 2 frame buffer IPs in our design. 1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Like I mentioned, I don't do much SOPC - designs, in fact I just dabbled a bit with it to find out out whether I could coerce/fit my interconnection scheme into an ST-compatible form which surprisingly worked out fine. But I haven't done a real SOPC-project yet.

I found the following in the Quartus II Handbook: Chapter 22: Avalon-ST Splitter Core

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Error Width : legal values 0–31 : Default 1 : The width of the error signal on the output interfaces. A value of 0 indicates that the error signal is not used. This parameter is disabled when Use Error is set to 0.

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