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Altera_Forum
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15 years ago

Frame buffer IP

We use 2 frame buffer IPs in our design. 1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We d...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you for your co-operation. I use the frame reader in my design with the following settings:

Bits per pixel per color plane: 8

Number of color planes in parallel: 3

Number of color planes in sequence: 1

Maximum Image width: 1920

Maximum Image height: 1080

Master port width: 64

Read master FIFO depth: 1024

Read master FIFO burst target: 64

Use separate clock for the Avalon MM master interface: unchecked

Kindly confirm if the following calculations for number the words and the Single Cycle Color Patterns are true or not

1- // Words

IOWR(FRAMEREADER_BASE, 5, 259200); // (1920*1080*8)/64 = 259200

2- // Single Cycle Color Patterns

IOWR(FRAMEREADER_BASE, 6, 2073600); // 1920*1080=2073600 number of pixels in the frame multiplied by the number of single cycles required to represent one pixel