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Altera_Forum
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10 years ago

FPP Configuration Timing: Clock Stop = high

We would like to configure a Cyclone V GX C5 using FPP via a TI DSP's EMIFA (External Memory Interface) bus (in Asynchronous mode). VC-52007 2015.12.21 Figure 7-3 mentions in note (5): If needed, pau...
Altera_Forum's avatar
Altera_Forum
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10 years ago

The important bit here is that there are no 'maximum' values specified for 'DCLK high time', 'DCLK low time' or 'DCLK period'. The passive programming methods are entirely synchronous, clocked by DCLK. Run and pause it as you wish.

Cheers,

Alex