FPGA Query

Depending on the version of the tools you are using, there are a few differences in how you get to the equivelent of the ".bit" file.

Basically, you can use the Create Project Wizard to get a project with a VHDL or Verilog source file (or schematic).

From there, you process the design to completion (Use the "PLAY" triangle in the tools bar at the top.).

Several steps will get executed if you have no errors along the way.

The Xilinx flow was something like this:

Syntax check then Synthesis,

Translate then Map, PAR, and finally makebits.

Use the Downloader to connect to the FPGA via JTAG, download the ".bit" file.

Done.

The Altera Flow is pretty much the same:

Process the design with the PLAY triangle will result in:

Syntax check and Synthesis.,

Fitter which is like Translate, MAP and PAR.

Assemble which is like Makebits.

End result is something called a ".sof" file. (Software object file I believe.)

Then you run the Programmer, (it should auto populate with the desired .sof file.)

Depending on if you already have a board with a part on it, and powered up and a JTAG cable connected, you may need to tell the programmer tool to "sniff" the board for your part (maybe in a chain of parts).

OK, so you might be asking how do awe make sure that we have the correct pins going to the correct place in the design so that when we download the design, the clock gets into the part, and the outputs wiggle the right I/O's.

Xilinx calls the file that controls this the .UCF file. (User Constraints file)

Altera calls the file that controls this the .QSF file. (Quartus Settings File)

You can use a tool called the Pin Planner to make the pin assignments.

It will save the pins that you "locate / place" into the .qsf file.

If you follow the tutorial provided with the tools or go to the training page on the Altera WEB site and watch the free Quartus II training class, you should have little problems getting it all done.

Welcome to the family, and keep us posted.