FPGA process LVDS serial differential ADC issue

Hello,

I think you will need to use dedicated clock input pins for DCO as if the DCO is used for the external clock input for your design. You can refer to the link below for reference:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/clocking-differential-receivers.html

As for Bank 2L, it is a 3V I/O bank which supports differential SSTL, HSTL, and HSUL I/O standards up to 3 V. For the LVDS, Intel Cyclone 10 GX supports it on all LVDS I/O banks. Refer to below links for more information:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/i-o-and-differential-i-o-buffers-in-devices.html

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/i-o-banks-groups-in-devices.html

Regards,

Aqid