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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

FPGA process LVDS serial differential ADC issue

Hi there, We are designing board's schematic. The board will use Cyclone 10 GX FPGA devices. Several AD9633 devices output LVDS serail differential pairs will be connected to this FPGA. We know th...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

first step is do decide about the synchronization method. It determines which ADC signals need to be connected and if they have to be routed to dedicated clock inputs.

If DCO is used as a clock in your design, it has to be routed to a dedicated clock input. If you want to use 10CX SERDES, only dedicated RX channels can be used, e.g. not bank 2L.