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Altera_Forum
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13 years ago

FPGA instability after reset

Hi all, I am working with a custom Cyclone IV E based HW that is suffering from strange startup instability. The HW runs fine under various stress tests and temperature ranges when programmed...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I've traced the system hangs to DDR calibration failure. The local_init_done signal from DDR stays 0 and ctl_cal_fail, ctl_init_fail are 1 when the boot hangs.

The DDR calibration fails only when deaserting reset too fast (< ~100ms) after FPGA configuration. DDR testing shown no errors under various conditions and

temperature ranges, so for now it looks like a reset issue only. The really strange behaviour I've noticed is that when the boot hangs it will continue to hang if

FPGA is reset by toggling nCONFIG, if the power is turned on/off quickly it will still hang, turning power off and waiting a minute gets the system a chance to

boot normally. Because of this I don't see any way out of boot hang even if I monitor the local_init_done. How is the local_init_done meant to be used, in

example designs I've seen it's left unconnected?