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Altera_Forum
Honored Contributor
15 years agoFmax is small, please, help me to improve it!
Hi, in my small systemverilog project (about 1000 lines) I have one module that is critical to the performance (I attached it below). This module takes 4x16 bit words (In) per clock (Clk),...
Altera_Forum
Honored Contributor
15 years agoIlghiz,
I think there is room for one further improvement: the lines ScalX2<=ScalX1+(ScalX1>>>SHR);
ScalX4<=ScalX3+Sum2; result in two reasonably large adders which probably cause the 'unstable' Fmax result. It would be a good idea to write a module that calculates the sum in two clocks in a split-manner: you add the lower halves of the input factors on the first clock while pipelining the upper halves, and adding these together with the carry-out of the first operation on the second clock edge. After that you probably can save a few pipeline stages in your module, as you will end up with a few back-to-back registers with no logic between them.