Fmax is small, please, help me to improve it!

Ilghiz,

Increasing Fmax further probably means messing up your nice code ...

To make full use of the registering inside the altmult_add blocks, now inferred by the synthesis of your source code, you actually have to use the Megawizard to define that block to your wishes, in this case for speed by enabling all pipeline registers inside the DSP block itself. That's the easy part, the hard work is now instantiating this block in your code. Unfortunately I only know very little Verilog, let alone System-Verilog, so I can't help you much here.

Later on you can replace the additions by calling lpm_add_sub (with pipelines), or by defining your own pipelined adder block. (I noticed failure paths in the N=18, SHR=14 compilation due to long adder chains as well).