Fmax is small, please, help me to improve it!

Your test.v shows the beauty and strength of real high level languages. But unfortunately this may also be a weakness when you target 'resource-fixed' architectures like FPGAs.

If you inspect the inferred altmult_add files and enter into the (lowest) .tdf file you will see that almost all ports are unregistered. The top line is very long, but if you edit it (by inserting carriage returns) you can see all the assumptions taken.

I recompiled (10.0 SP1 Web) for N=2 and SHR = 2, and failed timing by 28 ps only.

I you select an inferred altmult_add in the navigation window and locate it in the resource Property Editor, you can see that 'dataa[]' is unregistered but 'datab[]' is. In the TimeQuest failed path reports I can see that this not-registering 'dataa[]' accounts for 718 ps interconnect delay.