Fixed Point VHDL Support in Quartus

Hi,

I am doing my Final year project including the floating point calculation. Anyone here know how to convert floating point number into integer with using the floating point package float_pkg_c.vhdl ? I already tried with the code below (a simply floating point addition and convert the summation into integer) but it show me this error --> "Error (10454): VHDL syntax error at float_pkg_c.vhdl(4314): right bound of range must be a constant" .Anyone here can help me to solve it? thanks.

Code:

library ieee;

use ieee.std_logic_1164.all;

library ieee_proposed;

use ieee_proposed.fixed_float_types.all; -- ieee in the release

use ieee_proposed.float_pkg.all; -- ieee.float_pkg.all; in the release

entity round is port (

a, b : in std_logic_vector (31 downto 0);

Sum : out integer;

Clk, reset : in std_ulogic);

end round;

architecture RTL of round is

signal afp, bfp, Sumfp : float32; -- same as "float (8 downto 23)"

begin

afp <= to_float (a, afp); -- SLV to float, using afp' range

bfp <= to_float (b, bfp); -- SLV to float, using bfp' range

process (clk, reset)

begin

if reset = '1' then

Sumfp <= (others => '0');

elsif rising_edge (clk) then

Sumfp <= afp + bfp;

Sum <= to_integer (Sumfp,round_inf,true);

end if;

end process;

end RTL;