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Altera_Forum
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12 years ago

First time CPLD use questions - internal pull up resistor and clocking with Max 7000S

I've designed a video game controller using Altera Max 7000s and Quartus 2 using the BDF process. 1-Was I suppose to add a clock? I only have inputs and outputs and logic gates needed in the ...
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Altera_Forum
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12 years ago

Pull up resistors in FPGA and CPLD are not 'real' resistors. They are implemented with a biased MOSFETs, so their characteristic is dependent on the VCCIO voltage.

Usually the datasheet specifies a maximum sourced current, not the ohmic value which is commonly in the 10k to 100k range; that's why they are referred to as 'weak'.

I never used the Max7000 device and I don't have the datasheet here, so I can't tell you if the pull up feature is available.