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Altera_Forum
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12 years ago

First time CPLD use questions - internal pull up resistor and clocking with Max 7000S

I've designed a video game controller using Altera Max 7000s and Quartus 2 using the BDF process. 1-Was I suppose to add a clock? I only have inputs and outputs and logic gates needed in the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If you only use combinatorial logic, a clock is not strictly required. <-- great

However, in a typical design you have a least one register or a few synchronous functions, so you usually do need a clock. ,<-- None, here just a bunch of NAND, NOR, OR, NOT gates

I'm using Block Diagram / Schematic tool, when I add a input and then right click and go to properties. It allows me to set the 'default value' to either VCC or GND. Is this setting used for anything?

I want inputs and outputs to be pulled high internally. How do I do this?

Thanks