Honored Contributor
Honored ContributorIf a design involves a risk of deadlock condition, they are not avoided by adding functionless code, e.g. "others" in a case construct. The compiler is smart enough to remove it. A deadlock can e.g. occur with illegal states of a state machine, it can be triggered by an incorrect reset or a timing violation of the system clock or an asynchronous input signal. But your design has no stae machines, only binary counters without a risk of deadlock.
Regarding timing of ads_clock and mdata in your design. I see mainly two options: - specify exact timing constraints for the external signals with Time Quest timing analyzer - perform a hand calculation of the expectable mdata timing related to your system clock (clk20) and check if it can be safely received. If not, invert the output clock. Other options are e.g.to generate phase shifted ads_clock through a PLL and send it through general I/O pins. But I think, it's not reasonable for a slow 20 MHz clock.
