Filter & decimation implementation on AD7401

What do you mean by "specifying the timing correctly"?

I understand that the delay will be obviously more than 5ns, and that this is a common problem in interfacing external devices such as an ADC in our case. But unfortunately I really got confused with this, again...

Regarding the datasheet, it is mentioned that data is valid during the rising edge of MCLKIN, and max data access time is 25ns (after rising edge). At the point of introducing the recommended filter+decimation code, it is mentioned that data is read on the falling edge. Also, at the interface of the code, mdata is not driven by the system clock, but by itself (sensitivity list, only when mdata changes value ?!). In our code we drive mdata with clk20 at the rising edge.

Outputting the 20 MHz clock towards the ADC, concerning 5ns++ (???) delay, and doing the operations of interfacing/filter/decimation with system clock, how can we be sure that we will achieve correct data receiving - synchronization?

ads_clk <= clk20;

I'm really confused, sorry.

I agree that it is not necessary in our application to get correct values/samples from "system-boot" - in worst case scenario there will be only 3-4 distorted samples.

I closed every 'IF' block in our code with "else... NULL" operations, so this should be enough to avoid dead-lock. Also, we are going to implement a asynchronous hard-reset pushbutton.

Just because of curiosity, would it be difficult to implement an initialization?

Thank you so much!