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Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
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16 years ago

If you specify the timing correctly, Quartus timing analysis will care for it. 5 ns output delay is only part of the involved delay, the ADC has most likely more delay. The problem is common to interfacing external devices.

If you don't need correct measrements from the start, you don't need a reset with your design, I think. You have to check, if it has illegal states, that may cause a dead-lock.