Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I mean that the filter/decimation operations will be working with system clock, but data will arrive from the ADC on every falling edge of the clock we output from the FPGA, which has a ~5nsec delay. Could we maybe pass the clock through some delay before outputting it to the ADC so that the 2 clocks are identical? (Tried some NOTs, but unfortunately..)

Something else, what about initialization at system-boot? Do the signals and I/Os need something like an internal reset at the start?