Filter & decimation implementation on AD7401

FvM,

I was searching for a solution for the clock-output issue we have, and I ended up with PLLs.

I read in Cyclone Handbook about how to handle PLL features in Cyclone FPGAs, but I unfortunately found out that the 100-pin EP1C3 device used in PLUTO-II board does not support external clock output.

Could you come up with any other (perhaps tricky) solution about how we could drive the ADC from the FPGA, providing it the external 20MHz clock we feed to the board from the dedicated clock input pin?

I think we can output the clock from any I/O of the board to the ADC without PLL, but there will be a sync issue of the system clock and the clock feeding into the ADC, am I right?

Thank you for your help!