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Honored Contributor

13 years ago

FIFO to SGDMA, FIFO Stays FULL memory not written.

Hello all, still a little new to NIOS and avalon components, but I've been going at it for a few days and I'm a bit stumped. I setup an external counter being fed through a custom Avalon compon...

Altera_Forum

Honored Contributor

13 years ago

Partially solved, the write_master wasn't hooked up to the CSR on the dispatcher, I now see the memory changing. The only problem remaining is that it still does not want to fire the interrupt

Edit: Now also solved solved forgot to enable IRQ

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FIFO to SGDMA, FIFO Stays FULL memory not written.

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