Feasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LP

Hi Huang Ruiyi,

I came across an article from Macnica where it shows a credible, logic‑only data‑recovery technique on Cyclone 10 LP that you can adapt.

However, it does not prove 350 MHz feasibility.

This can be helpful as a conceptual starting point for you.

Reference:

https://www.macnicacytech.com/apac/cytech/en/technical-articles/using-cyclone10lp-device-achieve-data-recovery-serial-communication/

Regards,

Aqid

Hi Huang,
I implemented soft CDR in Cyclone 10 LP utilizing PLL dynamic phase shift (requires 1 PLL output per RX channel). I'm effectively using SDR sampling of input data stream, the other RX clock edge is used to detect and track data edge. According to design requirements, I didn't go above 250 MHz but 350 MHz should basically work.

Unfortunately I can't share implementation details.

Regards
Frank