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huangruiyi's avatar
huangruiyi
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1 day ago

Feasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LP

Hello,

For Cyclone 10LP, is it feasible to implement for LVDS soft-CDR Rx @ 350MHz? Does anyone has achieved this at this data rate (or lower data rate)?

Thank you very much.

Yours sincerely,

Huang Ruiyi

Core Logic

1 Reply

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 day ago

    Hi Huang,
    I implemented soft CDR in Cyclone 10 LP utilizing PLL dynamic phase shift (requires 1 PLL output per RX channel). I'm effectively using SDR sampling of input data stream, the other RX clock edge is used to detect and track data edge. According to design requirements, I didn't go above 250 MHz but 350 MHz should basically work.

    Unfortunately I can't share implementation details.

    Regards
    Frank