Forum Discussion
Occasional ContributorFailure on getting timing closure for custom transceiver (phy) interface + dcfifo
I am not sure why the hold violation is not optimized by the tool. I have tried to adjust the Fitter Advanced settings, but I was unable to resolve the hold violation.
However, I noticed that the setup for the failing timing path has a significant positive slack window. I used the set_min_delay SDC on those paths with timing violations to compensate for the hold window, and I was able to resolve the violation.
Attached the project and the SDC list used:
set_min_delay -2 -from [get_keepers {stmbus_fiber:stmbus_fiber_instance|tx_framer:stmbus_tx_framer|tx_framer_state.FRAMER_RESET_STATE}]
set_min_delay -2 -from [get_keepers {stmbus_fiber:stmbus_fiber_instance|tx_framer:stmbus_tx_framer|tx_framer_state.FRAMER_FINISH_STATE}]
set_min_delay -2 -from [get_keepers {stmbus_fiber:stmbus_fiber_instance|fifo_async_16x32:tx_fifo_async_16x32|dcfifo:dcfifo_component|dcfifo_6vn1:auto_generated|a_graycounter_bu6:rdptr_g1p|counter5a*}]
set_min_delay -2 -from [get_keepers {stmbus_fiber:stmbus_fiber_instance|tx_framer:stmbus_tx_framer|\tx_framer_process:framer_counter[*]}]
set_min_delay -2 -from [get_keepers {adcbus_fiber:adcbus_fiber_instance|tx_framer:adcbus_tx_framer|tx_framer_state.FRAMER_RESET_STATE}]
set_min_delay -2 -from [get_keepers {adcbus_fiber:adcbus_fiber_instance|tx_framer:adcbus_tx_framer|tx_framer_state.FRAMER_FINISH_STATE}]
set_min_delay -2 -from [get_keepers {adcbus_fiber:adcbus_fiber_instance|fifo_async_16x32:tx_fifo_async_16x32|dcfifo:dcfifo_component|dcfifo_6vn1:auto_generated|a_graycounter_bu6:rdptr_g1p|counter5a*}]
set_min_delay -2 -from [get_keepers {adcbus_fiber:adcbus_fiber_instance|tx_framer:adcbus_tx_framer|\tx_framer_process:framer_counter[*]}]
Other changes made:
- Disable all the assignment setting.
- Add the I/O SDC constraint for the bidirectional port.
Best Regards,
Richard Tan
Super ContributorMay I know if the failing timing path occurs in the Transceiver IP or the FPGA design?
If it is failing on the IP side, I will need to consult with the IP owner.
Could you please share your design by archiving the project (Project > Archive Project) so that I can investigate it further?
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
Occasional ContributorDear Richard,
I'm not sure but from the looks of it, it seems the FPGA design is what's failing. Could it be that somehow the
