Forum Discussion

binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

F-tile "Tile Interface planner" not showing legal locations for PCIe Streaming IP

Hi, I have two F-tile PCIe Streaming IPs in my design. I opened "Tile Interface Planner" to place these IPs to corresponding banks. But for some reason when I double click to see the legal locations...
Other Ips
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

Hi,

In a PCIe example design, you need to assign pin locations to hip rx/tx pins, e.g. hip_serial_tx_n_out0.

A easy way to assign all PCIe including related pins. You could select the top module, e.g. pcie_ed, then choose one of the legal locations shown as attached pcie_interface_planner_all_pins.png. This will complete all pins as shown in pcie_interface_planner_all_pins2.png.

Regards,

Rong

  • binupr's avatar
    binupr
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago
    Hi Rong,

    What I mentioned was a custom design and not Intel reference design. I already found the issue. Firstly the issue was that the tile planner didn’t show any legal locations. In my design I didn’t want all to assign all lanes in a PCIE IP. But Quartus doesn’t like it. Hence not showing legal allocations. There must be a way not to use all lanes in an IP. Let me know if you have idea on that.

    Btw, I have previously generated intel reference design for PCIe. You don’t have to assign hip tx or rx pins. The generated project already has the pins allocated.

    Regards
    BPR
    • RongY_altera's avatar
      RongY_altera
      Icon for Contributor rankContributor
      1 year ago

      There must be a way not to use all lanes in an IP.

      You mean to assign only partial pins of a 1x16 then use it like that?

      The PCIe can be downgraded when host has less lanes. Or you can set PCIe IP to 1x8 to use less lanes.

      Regards,

      Rong