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I am inputting an external clock from a GPS module (m12m timing receiver) into the DE1 board. I've measured it to be ~3V. The GPS module sends a pulse with a width of 200ms (very fast rise time) every 1 second.
My first problem is that the @(posedge) logic is sensitive to the rising and falling edge of this pulse. Secondly, there are times (in in 50 or thereabouts) where the positive edge isn't detected at all.
Does anyone have any tips or advice on how to get around this problem and make the setup more robust!
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First, use an oscilloscope and SignalTap II to look at the signal (with SignalTap II clocked by the on-board 50MHz clock). If the scope waveform looks bad (ringing/overshoot), then try and make it better. If SignalTap II traces show multiple pulses near the edges of the external signal, then that also indicates you have a bad clock termination resulting in reflections and ringing. Is the GPS clock output 50-ohm source terminated? If its high impedance, then you can try adding a 50-Ohm end-termination. Don't add both source and end, otherwise you get a voltage divider, so you'll only get a 3V/2 = 1.5V clock waveform (which might appear to work better - but its not really).
If you cannot clean up the external clock, and still get glitches, then you can 'deglitch' the signal using a small state machine to track that the signal stays at a particular logic level for a certain number of clocks before the 'deglitched' output changes.
See if you can fix the external clock first. If you can't then ask me for the deglitch filter code.
Cheers,
Dave
Honored Contributor
