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1. Why have to constant? and how does the time constraint work?
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VHDL describes what the logic does, however, it does not really define when and how fast it can do it, that is a function of the physical device. The same VHDL can run faster or slower depend on the FPGA you are using. If you have a particular frequency that you must operate at, then that is part of your FPGA selection process.
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2. Does It aply only for registers and clocks? what's about combintional logic, or group of logic?
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It applies to both registered and combinatorial logic. However, in some cases you don't care about a combinatorial path, so you can apply a timing constraint that indicates you do not care about that particular path.
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3. How can I constraint the large project with many sub-entity, hundred of logic gates, registers..
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Logic internal to the FPGA is generally constrained using a clock constraint.
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4. If I use the megafunction plugin, of which don't know the inner structure. (I don't know how many register, logic gate, clock are there and how do they connect...) So how can I constraint them? for example megacore: FFT, FIR, NCO...
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An FFT, FIR, or NCO has registers on the input and output, so that component is essentially internal to the FPGA, and is covered by a clock constraint. If you send the output of an NCO over to a DAC to generate a sinusoid external to your FPGA, then the signals going between the FPGA and the DAC need to have I/O constraints applied. These constraints are determined by the external device, i.e., the DAC, its input registers have setup and hold timing requirements. You use a timing constraint to tell the synthesis tool what those constraints are, and it programs the FPGA I/O delay elements to meet those requirements.
Cheers,
Dave
Honored Contributor
