New ContributorHi,
I'd like to implement a SIO in a MAX10 FPGA connected via eSPI to an Intel Atom CPU.
It is not really clear to me how to use the Intel eSPI Slave IP core for driving peripheral components like UARTs, GPIOs etc.
Has there anyone an example design or can explain in detail how I could to do this?
Thank you in advance
Wolfram
Regular ContributorHi WFitt,
There is no eSPI reference design for user as I know.
The source for user reference are from the documents as below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf
Thanks.
Regards,
Aik Eu
New ContributorHi aikeu,
Thank you for your reply!
I know these documents. But unfortunately there is no explanation how to go on with connection of peripheral devices like UARTs or GPIOs in detail.
Is there anyone who has used the eSPI IP core and can give me some support?
Regards
Wolfram
Regular ContributorHi WFitt,
Unfortunately, I am not aware of anyone who has used eSPI IP before in order to recommend for now.
We only have the documents to support on this particular IP.
Thanks.
Regards,
Aik Eu
New ContributorIs it possible that I am the only developer in the world who likes to use the Intel eSPI IPcore?
Regular ContributorHi WFitt,
There are customers who are using it in their design and I am not sure the full details of their design.
The support we provided to them is mainly on the communication protocol issues when they applied in their system. Example like provide them simulated test waveform for a specific type of transaction performed by the eSPI IP as their basic reference.
Thanks.
Regards,
Aik Eu
New ContributorThank you Aik!
It would be very helpful for me if you could provide a testbench for read and write access from / to a peripheral channel.
Regards
Wolfram
New ContributorCould you please provide testbenches and waveforms for the eSPI slave commands PUT_MEMRD32_SHORT & PUT_MEMWR32_SHORT
