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Honored Contributor
Honored ContributorErrors reading M9K dual port in Cyclone III
Hi, We are using four Megawizard generated dual ports in a 3C40F484C8. There are 128 locations, 24 bits wide, asynchronous write and read clocks. A common write_data and write_address bus goes to ...
Altera_ForumHonored Contributor
Honored ContributorI noticed your RAM is using an enable signal. Altera has discovered a problem with the Quartus 9.0 timing analysis of the M9K in CIII involving enable signals. Here's the solution id /rd04302009_15. There's a script you can run to diagnose if your design is at risk for the missing enable path in the Quartus timing analysis.
