I have a Stratix V design I'm trying to migrate to Quartus Prime Standard Edition 23.1 from 18.1. During compile (in the Analysis & Synthesis section), I encountered following error message: (12006): Node instance "altclkctrl_component" instantiates undefined entity "altclkctrl_inst". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP. My design doesnt call this component directly. When I clicked on the error message, it brought me to a file alt_sfl_enchanced.v which is located at the install directory: c:/intelfpga/23.1std/quartus/libraries/megafunctions/alt_sfl_enhanced.v. It look for that instance. Where is this instance suppose to reside, and how do I find it?

Easiest thing would be to either update the IP from the Project menu (do you have a yellow or red warning above the Hierarchy mentioning updating IP?) or delete and re-add the clock control block to your design.

I already updated all my IP components. There are no more yellow. See below screen shot.On the left site, it lists all the IP I use in my project. None of them directly instantiate the clock control block. Not sure which one I should delete and re-add.

It appears that there are code changes to the alt_sfl_enhanced.v file between these two versions of Quartus.I'm unsure about the reasons for these changes, and I may need to consult with the engineering team for clarification.Could you help to share the .qar design (Project > Archive Project) with us? We'll need to duplicate the error for the engineering team to investigate.Please provide the design files for both Quartus 18.1 and 23.1.If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP.Regards,Richard Tan

I actually manually edited alt_sfl_enhanced.v file at the install directory to comment out the few lines for the alclktrl_component. After that, compile was successful. But obviously we are not sure the repercussions of doing this editing since it's to be part of Intel IP. Please email me. we are working on a strip down version of the design to share with you.

Educated guess here. It sure looks like the"altclkctrl_inst altclkctrl_component"that was added to alt_sfl_enhanced.v some time ago was meant to be"altclkctrl altclkctrl_inst".Given that "altclkctrl" is an Altera megafunction that actually exists and matches the port list of the instantiation. And "altclkctrl_inst" would be a reasonable instance name.Note also that this change in alt_sfl_enhanced.v goes back a while, at least as far back as Quartus 21.1.1 (oldest version I had laying around to check).Engineering team perhaps missing a regression test for alt_sfl_enhanced.v?

Error Message 12006 with Quartus Prime Standard Edition 23.1

11 Replies

sstrell
Super Contributor
1 year ago
Easiest thing would be to either update the IP from the Project menu (do you have a yellow or red warning above the Hierarchy mentioning updating IP?) or delete and re-add the clock control block to your design.
IonTorrent
New Contributor
1 year ago
I already updated all my IP components. There are no more yellow. See below screen shot.
On the left site, it lists all the IP I use in my project. None of them directly instantiate the clock control block. Not sure which one I should delete and re-add.
RichardT_altera
Super Contributor
1 year ago
It appears that there are code changes to the alt_sfl_enhanced.v file between these two versions of Quartus.
I'm unsure about the reasons for these changes, and I may need to consult with the engineering team for clarification.
Could you help to share the .qar design (Project > Archive Project) with us? We'll need to duplicate the error for the engineering team to investigate.
Please provide the design files for both Quartus 18.1 and 23.1.
If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP.
Regards,
Richard Tan
- IonTorrent
  New Contributor
  1 year ago
  I actually manually edited alt_sfl_enhanced.v file at the install directory to comment out the few lines for the alclktrl_component. After that, compile was successful. But obviously we are not sure the repercussions of doing this editing since it's to be part of Intel IP. Please email me. we are working on a strip down version of the design to share with you.
- roeekalinsky
  Contributor
  1 year ago
  Educated guess here. It sure looks like the
  "altclkctrl_inst altclkctrl_component"
  that was added to alt_sfl_enhanced.v some time ago was meant to be
  "altclkctrl altclkctrl_inst".
  Given that "altclkctrl" is an Altera megafunction that actually exists and matches the port list of the instantiation. And "altclkctrl_inst" would be a reasonable instance name.
  Note also that this change in alt_sfl_enhanced.v goes back a while, at least as far back as Quartus 21.1.1 (oldest version I had laying around to check).
  Engineering team perhaps missing a regression test for alt_sfl_enhanced.v?
RichardT_altera
Super Contributor
1 year ago
I have send you an email. Please kindly check and attach the design.
Thank you.
RichardT_altera
Super Contributor
1 year ago
As mentioned in the email, I able to duplicate the issue and have submitted a case to the engineering team to investigate.
Please keep in mind that any work involving our engineering team may take some time, ranging from a few days to a few weeks, depending on the complexity of the issue.
We appreciate your understanding and patience regarding this matter.
I will keep you updated as soon as there is any progress or findings.
Regards,
Richard Tan
RichardT_altera
Super Contributor
1 year ago
The engineering team is still investigating the issue.
I will continue to follow up with the engineering team and provide you with an update as soon as possible.

Regards,
Richard Tan
RichardT_altera
Super Contributor
1 year ago
I just wanted to inform you that I'm working closely with the engineering team to evaluate this issue and assess any associated risks.
RichardT_altera
Super Contributor
1 year ago
The engineering team does not recommend reverting the SFL logic, as doing so may lead to unnecessary pulses or glitches, as mentioned in the following KDB article: https://www.intel.com/content/www/us/en/support/programmable/articles/000088178.html.

Users will need to add the altclkctrl module to their design.

Or

Recommend those who are using SFL IP to upgrade from older versions.

Regards,
Richard Tan
RichardT_altera
Super Contributor
1 year ago
I will file a KDB for this in case other customer may come across a similar issue.
With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.
Thank you and have a great day!
Edit:
KDB published : https://www.intel.com/content/www/us/en/support/programmable/articles/000098731.html

Best Regards,
Richard Tan

Forum Discussion

Error Message 12006 with Quartus Prime Standard Edition 23.1

11 Replies

Recent Discussions

MAX10 fiftyfivenm encrypted module

Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered

Stratix 10 CKEXT Drive Level 32 GHz Clock

QSPI DDR Interface with Cyclone10LP: Maximum frequency

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)