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Altera_Forum
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14 years ago

Error (10533): VHDL Wait Statement error

Hi, I called in a CPRI IP from Altera Quartus II which created a testbench tb_altera_cpri. While trying to compile this testbench I encountered an error: Error (10533): VHDL Wait ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Quartus tells you, that this wait syntax isn't supported for synthesis.

The sensitivity list should be specified with the process statement. In case of doubt refer to the VHDL templates accessible in the Quartus editor. According to the code, only reset and clock are meaningful members of the sensitivity list.

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thank , problem solved !