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Yes. Its line 839.
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We both know that. I wanted you to post the code so I could confirm it was valid VHDL.
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Is it anyway possible to look at the RTL viewer using this testbench?
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The RTL viewer is a Quartus tool, so no, you cannot view the testbench using RTL viewer. Viewing a testbench makes no sense, given that most of the logic does not create RTL. Testbenches contain non-synthesizeable constructs.
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I tried compiling with ModelSim, I faced another error saying,
"Error: Error loading design # Pausing macro execution # MACRO ./compile_vhdl.do PAUSED at line 65"
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I haven't seen that one before. How are you trying to simulate in Modelsim - using Nativelink or from within Modelsim directly?
Cheers,
Dave
Honored Contributor
