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Altera_Forum's avatar
Altera_Forum
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14 years ago

EP3CXX Pin Migration

I'm sorry for yet another question about migrating between devices in the same family, but I've not been able to find an explicit answer to my question on the Forum.

In migrating between, say, an EP3C5 and EP3C25 it's clear that some I/O pins on the EP3C5 will be used as GND/VCCINT on the EP3C25. If I connect these pins to GND/VCCINT in my design and then populate the board with an EP3C5, then some I/O pins with a VCCIO of 3.3V will be connected to 1.2V (VCCINT). Is this OK? Isn't this an indeterminate logic level? Many CMOS devices don't like this kind of thing and may draw excessive current.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Bigger FPGA needs more power. Yeah, you can set to MAX in Current Strength.

    Sean
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    In Quartus II, you can select migration devices for your design, and it returns you the preferred connections for all selected devices.

    I assume there should be compilation warnings if pins are set to inappropriate levels?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thank you. Your response made me take a closer look at the pin planner where I noticed something that had escaped me before. It directs me to connect these pins to VCCINT even when I compile for an EP3C5 device. It must therefore be OK to do so.