dynamic reconfiguration on stratix V FPGAs logic region not transceivers

hey hi

can any one here explain or provide me an idea/tutorial on how to perform dynamic partial reconfiguration in altera stratix V FPGAs using quartus II 11.0. I am looking for the dynamic reconfiguration of the logic region not the transceivers. Something similar to the xilinx virtex fpgas

Thanks,

shayan sengupta.