Dual port Fifo with 400MHz

Sounds like ADS5474.

I don't intend to work out the design details, but it's most likely necessary to perform the 1:2 demultiplex directly at the LVDS

inputs with an altddio_in function, using DRY as aquisition clock. If I understand right, Cyclone III C8 isn't able to provide a

400 MHz output clock. However, to utilize the ADC performance specification, a low jitter external clock should be used anyway.

The clock jitter of a FPGA PLL output (with FPGA families that support 400 MHz clock output) would be unsuitably high anyway.

Considering the ADC prices, a higher performance FPGA should still fit the design, I think. But as far as I see, it can work with Cyclone III.