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TomM's avatar
TomM
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5 years ago

Dual Configuration IP on MAX10

Hi, I have got a problem with the Dual Configuration IP on a Max 10M08DAF256I7G. I'm using Quartus Version 17.1. I write the config_sel_overwrite and config_sel at Offset 1 Read the busy signal ...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


May I know what is the clk frequency that you are using and what is the setting used on the dual configuration IP?


  • TomM's avatar
    TomM
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    the clock frequency is 40 MHz. This is also set in the dual config IP (see attached screenshot).

    There is also a design contraint set for the clock

    create_generated_clock -name ru_clk -divide_by 2 -master_clock PLL|altpll_component|auto_generated|pll1|clk[1] -source [get_pins -compatibility_mode { *altera_dual_boot:dual_boot_0|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_clk|clk }] [get_pins -compatibility_mode { *altera_dual_boot:dual_boot_0|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_clk|q } ]