DQS Input and Output Timing Constraints

Clocks that you need:

input side: virtual clock (clock that drives the data from "upstream" device; use create_clock with no target), base clock (clock that arrives at FPGA from upstream device; use create_clock), PLL-generated clock that captures the data (from derive_pll_clocks)

output side: PLL-generated clock that launches the data (from derive_pll_clocks), generated clock targeted at clock output port and sourced from PLL (relationship to source is -multiply_by 1)

I never said to not use derive_pll_clocks. You just need to use it along with the other clock constraints I've listed.

You don't want or need the multicycle. On the input side, the problem is you're missing the virtual clock.

You also need set_false_path timing exceptions to prevent the timing analyzer from performing analysis that is not relevant to your design. I'm guessing you want center-aligned, same edge analysis (launch on rising edge, latch on rising edge; fall to fall too), so you would have set_false_path exceptions that prevent rise to fall and fall to rise analysis.

Again, check out the online training. It spells all of this out.