DQS Input and Output Timing Constraints

The multicycle path 0 was because, in my understanding, the input pin was both the launch clock and the latch clock, as opposed to there being a "data was launched on the previous clock cycle, latched on the next clock cycle." This might be unnecessary, or an alternate way of doing this, or (most likely) I'm just super confused.

I do have derive_pll_clocks defined. You say that "your generated clock on the output looks correct.", but I'm seeing a 0-degree phase in TimeQuest (see attached).

I would expect to see the launch clock at 0 degrees, and the latch clock at 90 degrees based on how I've design the dq vs dqs timing.

So either my constraints are wrong, or how I'm interpreting the the timequest waveform is wrong.