Honored Contributor
Honored ContributorWhat's the multicycle of 0 for? That only gets used on the output in the edge-aligned case to account for data capture at the "downstream" device.
Do you have a derive_pll_clocks somewhere that you're not showing here? That's why you would get the error about multiple clocks on the same node. Your generated clock on the output looks correct. My guess is you're using derive_pll_clocks, creating double clocks, causing the warning and error. Generate a clock report in the timing analyzer to see what clocks have been created by your sdc. See this online training for details on constraining a DDR source synchronous interface: https://www.altera.com/support/training/course/oddr1000.html
